? semiconductor components industries, llc, 2009 march, 2009 ? rev. 3 1 publication order number: nbxdda016/d nbxdda016, NBXDDB016 3.3 v, 133.33 mhz /137.93 mhz dual frequency cml clock oscillator the NBXDDB016/nbxdda016 dual frequency crystal oscillator (xo) is designed to meet today?s requirements for 3.3 v cml clock generation applications. the device uses a high q fundamental crystal and phase lock loop (pll) multiplier to provide selectable 133.33 mhz or 137.93 mhz, ultra low jitter and phase noise cml differential output. this device is a member of on semiconductor?s pureedge clock family that provides accurate and precision clock solutions. available in 5 mm x 7 mm smd (clcc) package on 16 mm tape and reel in quantities of 1,000. frequency stability options available as either 50 ppm NBXDDB016 or 20 ppm nbxdda016. features ? cml differential output ? uses high q fundamental mode crystal and pll multiplier ? ultra low jitter and phase noise ? 0.4 ps (12 khz ? 20 mhz) ? selectable output frequency ? 133.33 mhz (default)/137.93 mhz ? hermetically sealed ceramic smd package ? rohs compliant ? operating range 3.3 v 10% ? total frequency stability ? 20 ppm or 50 ppm applications ? high ? end servers ? basestation ? general purpose clock generation and margining figure 1. simplified logic diagram pll clock multiplier crystal gnd fsel oe clk clk v dd 654 123 http://onsemi.com device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. NBXDDB016ln1tag* clcc ? 6 (pb ? free) 1000/ tape & reel marking diagrams nbxdda016 = nbxdda016 ( 50 ppm) NBXDDB016 = NBXDDB016 ( 20 ppm) 133.33/137.93 = output frequency (mhz) a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 6 pin clcc ln suffix case 848ab NBXDDB016 133.33/137.93 awlyywwg nbxdda016ln1tag clcc ? 6 (pb ? free) 1000/ tape & reel nbxdda016 133.33/137.93 awlyywwg * please contact sales office for availability nbxdda016lnhtag clcc ? 6 (pb ? free) 100/ tape & reel
nbxdda016, NBXDDB016 http://onsemi.com 2 figure 2. pin connections (top view) fsel oe gnd clk v dd clk 1 2 3 6 5 4 table 1. pin description pin no. symbol i/o description 1 oe lvttl/lvcmos control input output enable pin. when left floating pin defaults to logic high and output is active. see oe pin description table 2. 2 fsel control input output frequency select pin. pin will default low when left open. see output fre- quency select table 3. 3 gnd power supply ground 0 v. 4 clk cml output non ? inverted clock output. typically loaded with 50 receiver termination resistor to v tt = v dd . 5 clk cml output inverted clock output. typically loaded with 50 receiver termination resistor to v tt = v dd . 6 v dd power supply positive power supply voltage. voltage should not exceed 3.3 v 10%. table 2. output enable tri ? state function oe pin output pins open active high level active low level high z table 3. output frequency select fsel pin output frequency (mhz) open (pin will float low) 133.33 high level 137.93 low level 133.33 table 4. attributes characteristic value input default state resistor 170 k esd protection human body model machine model 2 kv 200 v meets or exceeds jedec standard eia/jesd78 ic latchup test 1. for additional moisture sensitivity information, refer to application note and8003/d. table 5. maximum ratings symbol parameter condition 1 condition 2 rating units v dd positive power supply gnd = 0 v 4.6 v t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 55 to +120 c t sol wave solder see figure 6 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
nbxdda016, NBXDDB016 http://onsemi.com 3 table 6. dc characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) (note 2) symbol characteristic conditions min. typ. max. units i dd power supply current (note 2) 70 100 ma v ih oe input high voltage 2000 v dd mv v il oe input low voltage gnd ? 300 800 mv i ih input high current oe fsel ? 100 ? 100 +100 +100 a i il input low current oe fsel ? 100 ? 100 +100 +100 a v ih fsel input high voltage 2000 v dd mv v il fsel input low voltage 0 800 mv v oh output high voltage (note 2) v dd ? 40 v dd mv v ol output low voltage (note 2) v dd ? 450 v dd ? 380 v dd ? 300 mv v outpp output voltage amplitude (note 2) 380 mv note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 ifpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. measurement taken with outputs terminated with 50 ohm to v dd . see figure 5.
nbxdda016, NBXDDB016 http://onsemi.com 4 table 7. ac characteristics (v dd = 3.3 v 10%, gnd = 0 v, t a = ? 40 c to +85 c) (note 3) symbol characteristic conditions min. typ. max. units f clkout output clock frequency fsel = high 137.93 mhz fsel = low 133.33 f frequency stability ? NBXDDB016 frequency stability ? nbxdda016 (note 4) 20 50 ppm noise phase ? noise performance 100 hz of carrier ? 102 dbc/hz f clkout = 133.33 mhz/137.93 mhz (see figures 3 and 4) 1 khz of carrier ? 120 dbc/hz 10 khz of carrier ? 126 dbc/hz 100 khz of carrier ? 126 dbc/hz 1 mhz of carrier ? 134 dbc/hz 10 mhz of carrier ? 162 dbc/hz t jit ( ) rms phase jitter 12 khz to 20 mhz 0.4 0.9 ps t jitter cycle to cycle, rms 1000 cycles 1.5 8 ps cycle to cycle, peak ? to ? peak 1000 cycles 10 30 ps period, rms 10,000 cycles 0.8 4 ps period, peak ? to ? peak 10,000 cycles 7 20 ps t oe/od output enable/disable time 200 ns t duty_cycle output clock duty cycle (measured at cross point) 48 50 52 % t r output rise time (20% and 80%) 160 300 ps t f output fall time (80% and 20%) 160 300 ps t start start ? up time 1 5 ms aging 1 st year 3 ppm every year after 1 st 1 ppm note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 ifpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. measurement taken with outputs terminated with 50 ohm to v dd . see figure 5. 4. parameter guarantees 10 years of aging. includes initial stability at 25 c, shock, vibration, and first year aging. figure 3. typical phase noise plot @ 133.33 mhz figure 4. typical phase noise plot @ 137.93 mhz
nbxdda016, NBXDDB016 http://onsemi.com 5 table 8. reliability compliance parameter standard method shock ? std ? 833, method 2002, condition b ? std ? 833, method 2003 ? std ? 833, method 2007, condition a ? std ? 202, method 215 ? std ? 833, method 1011, condition a c per ipc/jedec j ? std ? 020d driver device receiver device clk d figure 5. typical cml termination for output driver and device evaluation (see application note and8173 ? termination of cml devices) clk d v tt = v dd 50 50 z = 50 z = 50 NBXDDB016/nbxdda016 260 217 175 150 temperature ( c) temp. 260 c 20 ? 40 sec. max. time 60 180 sec. 3 c/sec. max. cooling 6 c/sec. max. 60 150 sec. reflow peak pre ? heat ramp ? up figure 6. recommended reflow soldering profile
nbxdda016, NBXDDB016 http://onsemi.com 6 package dimensions 6 pin clcc, 7x5, 2.54p case 848ab ? 01 issue c *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* pitch 2.54 1.50 6x 5.06 1.50 6x dimension: millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b e 6x 0.10 b 0.05 a c c 0.15 c terminal 1 indicator top view a a1 a3 0.10 c c seating plane side view l 6x 1 2 5 6 d3 dim a min nom max millimeters 1.70 1.80 1.90 a1 0.70 ref b 1.30 1.40 1.50 d1 6.17 6.20 6.23 d2 6.66 6.81 6.96 e1 4.37 4.40 4.43 r 0.70 ref l 1.17 1.27 1.37 a2 0.36 ref a3 0.08 0.10 0.12 d 7.00 bsc d3 5.08 bsc e 5.00 bsc e2 4.65 4.80 4.95 e3 3.49 bsc e 2.54 bsc d1 e1 d2 e2 a2 3 4 e3 r 4x h on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 nbxdda016/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative
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